In general, CMOS semi-conductor devices include integrated circuits having complementary pairs of P-channel field-effect transistors and M-channel field-effect transistors formed on a common semiconductor substrate. As is generally known in the art, CMOS technologies are typically used to fabricate IC (integrated circuit) chips for high density and high-performance applications due to, e.g., the high operation efficiency, high switching speed, and good scaling properties that are characteristic of CMOS devices. Technological innovations in semiconductor fabrication technologies are driving market demands for CMOS solutions for higher speed, higher integration density, and lower power applications. The downscaling of CMOS technologies to submicron design rules and beyond, however, poses technological challenges with respect to maintaining performance and reliability. For example, as device sizes are downscaled, CMOS transistors must be formed with, e.g., thinner gate electrodes, smaller channel lengths, and shallower drain/source extension diffusion regions. This downscaling generally results in transistors having higher channel resistance and higher junction/contact parasitic resistances, leading to degraded performance. To mitigate the impact on device performance with downscaling, various state of the art CMOS fabrication techniques can be implemented to effectively reduce parasitic gate and junction resistances and increase channel conductivity.
For example, DSL (dual stress liner) techniques can be incorporated in CMOS process flows as a means to enhance performance of highly-scaled CMOS devices. In general, DSL technologies are premised on findings that the application of a sufficient compressive stress to the conduction channel of a P-type transistor can improve the carrier (holes) mobility within the channel, while the application of a sufficient tensile stress to the conduction channel of an N-type transistor can improve the carrier (electrons) mobility within the channel. In this regard, various DSL techniques that have been developed to improve device performance by forming a compressive stress insulating liner over the gate structure of P-type transistors while forming tensile stress insulating liners over the gate structures of N-type transistor devices, for the purposes of increasing the charge carrier mobility in the transistor channels.
Other state of the art CMOS fabrication processes for increasing transistor performance in highly-scaled applications include ion implantation techniques that are designed to form complex dopant profiles/structures for drain/source regions, which effectively reduce the sheet and contact resistances of the transistor channel/junction/contact regions. Moreover, CMOS fabrication processes can implement state of the art Salicide (self-aligned silicide) technologies for silicidation of polysilicon gate structures and source and drain diffusion regions to thereby reduce gate and junction resistances.
In general, ion implantation and salicide techniques are typically implemented in conjunction with spacer fabrication techniques to form insulating spacers on the sidewalls of gate electrodes that serve as masks for ion implantation and salicidation. By way of specific example, nitride spacers are typically formed on the sidewalls of a gate electrode to serve as masks to control ion implantation profiles of source/drain regions offset from the edges of the gate electrode. Moreover, nitride spacers serve as masks to form metal silicide layers on polysilicon gate electrodes and drain/source diffusion regions in a self-aligned fashion. Although gate sidewall spacer elements facilitate ion implantation and salicidation, these spacers are typically designed to optimize ion implantation and salicidation processes, but not other processes. In this regard, the use of spacer elements and/or the process of forming such spacers, can adversely affect other process steps, resulting in degraded performance or reliability, or other pose practical limitations on integration density.
For example, as CMOS devices scale down and the critical dimensions of the gate electrodes decrease (smaller gate length and spacing between gate stacks), the gate sidewall spacers pose a limitation to integration density. Indeed, for a given design rule, the sidewall spacers effectively increase the width of the gate stack structure and narrow the spacing (gaps) between adjacent transistor devices. In other words, for a given design rule, the gate sidewall spacers increase the aspect ratio of the gaps between the gate structures, and such increased aspect ratio can render subsequent deposition based processing steps more difficult. For example, the spacers may adversely affect gap filling ability of a subsequent inter-layer dielectric (ILD) layer deposition.
In addition, the use of gate sidewall spacers can be problematic in DSL applications. For example, in high-density applications where the thickness of the spacers further narrows the spacing between adjacent transistor devices, there may be limitations on the allowable thickness of the dielectric stress liner layers that can be achieved to obtain a desired stress characteristic. Moreover, in DSL and non-DSL applications, the gate sidewall spacers may impart unwanted stresses in the transistor channel regions, which can counteract the desired stresses provided by the stress liner layers (for DSL applications), thereby adversely affecting performance. Therefore, for certain applications, it is desirable to remove the gate side wall spacers.